View NB639DL_7616807.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

nb639 high efficiency, fast transient, 8a, 28v synchronous step-down converter in a tiny qfn20 (3x4mm) package nb639 rev.1.13 www.monolithicpower.com 1 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. the future of analog ic technology description the nb639 is a fully integrated, high frequency synchronous rectified step-down switch mode converter. it offers a very compact solution to achieve 8a continuous output current over a wide input supply range with excellent load and line regulation. the nb639 operates at high efficiency over a wide output current load range. to further optimize efficiency at light load, this device?s v cc supply is designed to be biased externally. constant-on-time (cot) control mode provides fast transient response and eases loop stabilization. full protection features include scp, ocp, ovp, uvp and thermal shutdown. the nb639 requires a minimum number of readily available standard external components and is available in a space-saving qfn20 (3x4mm) package. features ? wide 4.5v to 28v operating input range ? 8a output current ? internal 30m ? high-side, 12m ? low-side power mosfets ? proprietary switching loss reduction technique ? 1% reference voltage ? programmable soft start time ? soft shutdown ? programmable switching frequency ? scp, ocp, ovp, uvp protection and thermal shutdown ? output adjustable from 0.8v to 13v ? available in a qfn20 (3x4mm) package applications ? notebook systems and i/o power ? networking systems ? optical communication systems ? distributed power pol systems all mps parts are lead-free and adhere to the rohs directive. for mps green status, please visit mps website under quality assurance. ?mps? and ?the future of analog ic technology? are registered trademarks o f monolithic power systems, inc. typical application
nb639 ? high efficiency, fast transie nt synchronous step-down converter nb639 rev.1.13 www.monolithicpower.com 2 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. ordering information part number* package top marking NB639DL qfn20 (3x4mm) 639 * for tape & reel, add suffix ?z (e.g. NB639DL?z) for rohs compliant packaging, add suffix ?lf (e.g. NB639DL?lf?z) package reference top view 1 2 3 4 5 6 16 15 14 13 12 agnd freq fb ss en pgood pgnd pgnd pgnd pgnd pgnd pgnd sw sw bst exposed pad on backside in sw sw vcc in in in in sw sw 78910 11 20 19 18 17 absolute maxi mum ratings (1) supply voltage v in ....................................... 30v supply voltage v cc ........................................ 6v v sw ........................................-0.3v to v in + 0.3v v bst ...................................................... v sw + 6v i vin (rms) ........................................................ 3.5a v pgood ...................................-0.3v to v cc +0.6v all other pins ..................................-0.3v to +6v continuous power dissipation (t a = +25c) (2) ???????????????????.2.6w junction temperature ...............................150 c lead temperature ....................................260 c storage temperature............... -65 c to +150 c recommended operating conditions (3) supply voltage v in ...........................4.5v to 28v supply voltage v cc ........................................ 5v output voltage v out .........................0.8v to 13v operating junction temp. (t j ). -40c to +125c thermal resistance (4) ja jc qfn20 (3x4mm) ......................48 ...... 10 ... c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max)=(t j (max)- t a )/ ja . exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb.
nb639 ? high efficiency, fast transie nt synchronous step-down converter nb639 rev.1.13 www.monolithicpower.com 3 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. electrical characteristics v in = 12v, v cc =5v, t a = +25 c, unless otherwise noted. parameters symbol condition min typ max units input supply current (shutdown) i in v en = 0v 0 a input supply current (quiescent) i in v en = 2v, v fb = 1v 40 a v cc supply current (quiescent) ivcc v en = 2v, v fb = 1v 350 a hs switch on resistance (5) hs rds-on 30 m ? ls switch on resistance (5) ls rds-on 12 m ? switch leakage sw lkg v en = 0v, v sw = 0v or 12v 0 10 a current limit i limit 16.5 a one-shot on time t on r freq =348k ? , v out =1.05v 360 ns minimum off time (5) t off 100 ns fold-back off time (5) t fb i lim =1 (high) 7.5 s ocp hold-off time (5) t oc i lim =1 (high) 40 s feedback voltage v fb 807 815 823 mv feedback current i fb v fb = 815mv 10 50 na soft start charging current +i ss v ss =0v 8.5 a soft stop discharging current -i ss v ss =0.815v 8.5 a power good rising threshold pgood vth - hi 0.9 v fb power good falling threshold pgood vth - lo 0.85 v fb power good rising delay t pgood tss = 1ms 1 ms power good rising delay t pgood tss = 2ms 1.5 ms power good rising delay t pgood tss = 3ms 2 ms en rising threshold en vth-hi 1.05 1.35 1.60 v en threshold hysteresis en vth-hys 250 420 550 mv en input current i en v en = 2v 2 a v cc under-voltage lockout threshold rising v cc uv vth 3.8 4.0 4.2 v v cc under-voltage lockout threshold hysteresis v cc uv hys 880 mv v out over-voltage protection threshold v ovp 1.25 v fb v out under-voltage detection threshold v uvp 0.7 v fb thermal shutdown t sd 150 c thermal shutdown hysteresis t sd-hys 25 c notes: 5) guaranteed by design.
nb639 ? high efficiency, fast transie nt synchronous step-down converter nb639 rev.1.13 www.monolithicpower.com 4 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. pin functions pin # name description 1 agnd analog ground. 2 freq frequency set during ccm operation. the on period is determined by the input voltage and the frequency-set resistor conne cted to freq pin. connect a resistor to in for line feed-forward. decouple with a 1nf capacitor. 3 fb feedback. an external resistor divider fr om the output to gnd, tapped to the fb pin, sets the output voltage. 4 ss soft start. connect an external ss capacito r to program the soft start time for the switch mode regulator. when the en pin becomes high, an internal current source (8.5ua) charges up the ss capacitor and t he ss voltage slowly ramps up from 0 to v fb smoothly. when the en pin becomes low, an internal current source (8.5 a ) discharges the ss capacitor and the ss voltage slowly ramps down. 5 en en=1 to enable the nb639. for automatic start-up, connect en pin to in with a 100k ? resistor. it includes an internal 1m ? pull-down resistor. 6 pgood power good output. the output of this pin is an open drain and is high if the output voltage is higher than 90% of the nominal voltage. there is delay from fb 90% to pgood high, which is 50% of ss time plus 0.5ms. 7 bst bootstrap. a capacitor connected between sw and bs pins is required to form a floating supply across the high-side switch driver. 8, 19 in supply voltage. the nb639 operates from a +4.5v to +28v input rail. c1 is needed to decouple the input rail. use wide pcb traces and multiple vias to make the connection. 9, 10, 17, 18 sw switch output. use wide pcb trac es and multiple vias to make the connection. 11-16 pgnd system ground. this pin is the referenc e ground of the regulated output voltage. for this reason care must be taken in pcb layout. 20 vcc external 5v supply. this 5v supply has to be applied in order to bias the device. decouple with a 1f capacitor as close to this pin as possible.
nb639 ? high efficiency, fast transie nt synchronous step-down converter nb639 rev.1.13 www.monolithicpower.com 5 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics v in =12v, v out =1.05v, l=1.0h, t a =+25c, unless otherwise noted.
nb639 ? high efficiency, fast transie nt synchronous step-down converter nb639 rev.1.13 www.monolithicpower.com 6 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics (continued) v in =12v, v out =1.05v, l=1.0h, t a =+25c, unless otherwise noted.
nb639 ? high efficiency, fast transie nt synchronous step-down converter nb639 rev.1.13 www.monolithicpower.com 7 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics (continued) v in =12v, v out =1.05v, l=1.0h, t a =+25c, unless otherwise noted.
nb639 ? high efficiency, fast transie nt synchronous step-down converter nb639 rev.1.13 www.monolithicpower.com 8 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. block diagram figure 1?functional block diagram
nb639 ? high efficiency, fast transie nt synchronous step-down converter nb639 rev.1.13 www.monolithicpower.com 9 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. operation pwm operation the nb639 is a fully integrated synchronous rectified step-down switch mode converter. constant-on-time (cot) control is employed to provide fast transient response and easy loop stabilization. at the beginning of each cycle, the high-side mosfet (hs-fet) is turned on when the feedback voltage (v fb ) is below the reference voltage (v ref ) which indicates insufficient output voltage. the on period is determined by the input voltage and the frequency-set resistor as follows: freq on in 12 r (k ) t(ns) v(v) 0.4 = ? (1) after the on period elapses, the hs-fet is turned off, or becomes off state. it is turned on again when v fb drops below v ref . by repeating operation this way, the converter regulates the output voltage. the integrated low-side mosfet (ls-fet) is turned on when the hs-fet is in its off state to minimize the conduction loss. there will be a dead short between input and gnd if both hs-fet and ls-fet are turned on at the same time. it?s called shoot-through. in order to avoid shoot-through, a dead-time (dt) is internally generated between hs-fet off and ls- fet on, or ls-fet off and hs-fet on. heavy-load operation figure 2?heavy load operation as figure 2 shows, when the output current is high, the hs-fet and ls-fet repeat on/off as described above. in this operation, the inductor current will never go to zero. it?s called continuous-conduction-mode (ccm) operation. in ccm operation, the switching frequency (f sw ) is fairly constant. light-load operation when the load current decreases, the nb639 reduces the switching frequency automatically to maintain high efficiency. the light load operation is shown in figure 3. the v fb does not reach v ref when the inductor current is approaching zero. as the output current reduces from heavy- load condition, the inductor current also decreases, and eventually comes close to zero. the ls-fet driver turns into tri-state (high z) whenever the inductor current reaches zero level. a current modulator takes over the control of ls- fet and limits the inductor current to less than 600 a. hence, the output capacitors discharge slowly to gnd through ls-fet as well as r1 and r2. as a result, the efficiency at light load condition is greatly improved. at light load condition, the hs-fet is not turned on as frequently as at heavy load condition. this is called skip mode. figure 3?light load operation as the output current increases from the light load condition, the time period within which the current modulator regulates becomes shorter. the hs-fet is turned on more frequently. hence, the switching frequency increases correspondingly. the output current reaches the critical level when the current modulator time is zero. the critical level of the output current is determined as follows:
nb639 ? high efficiency, fast transie nt synchronous step-down converter nb639 rev.1.13 www.monolithicpower.com 10 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. in out out out sw in (v v ) v i 2lf v ? = (2) it turns into pwm mode once the output current exceeds the critical level. after that, the switching frequency stays fairly constant over the output current range. switching frequency constant-on-time (cot) control is used in the nb639 and there is no dedicated oscillator in the ic. the input voltage is feed-forwarded to the on- time one-shot timer through the resistor r freq . the duty ratio is kept as v out /v in . hence, the switching frequency is fairly constant over the input voltage range. the switching frequency can be set as follows: 6 sw freq in delay in out 10 f(khz) 12 r (k ) v(v) t(ns) v(v) 0.4 v (v) = + ? (3) where t delay is the comparator delay. it?s about 40ns. nb639 is optimized to operate at high switching frequency with high efficiency. high switching frequency makes it possible to utilize small sized lc filter components to save system pcb space. ramp compensation figure 4 and figure 5 show jitter occurring in both pwm mode and skip mode. when there is noise in the v fb downward slope, the on time of the hs-fet driver deviates from its intended location and produces jitter. it is necessary to understand that there is a relationship between a system?s stability and the steepness of the v fb ripple?s downward slope. the slope steepness of the v fb ripple dominates in noise immunity. the magnitude of the v fb ripple doesn?t affect the noise immunity directly. v re f v fb hs dr i ver v noise jitter v slo pe1 figure 4?jitter in pwm mode v fb hs dr i ver jitter v ref v slo pe2 v noise figure 5?jitter in skip mode when the output capacitors are ceramic ones, the esr ripple is not high enough to stabilize the system, and external ramp compensation is needed. i i fb i c4 i r4 i fb figure 6?simplified circuit in pwm mode with external ramp compensation in pwm mode, an equivalent circuit with hs-fet off and the use of an external ramp compensation circuit (r4, c4) is simplified in figure 6. the external ramp is derived from the inductor ripple current. if one chooses c4, r1, and r2 to meet the following condition:
nb639 ? high efficiency, fast transie nt synchronous step-down converter nb639 rev.1.13 www.monolithicpower.com 11 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. 12 sw 4 1 2 rr 11 2f c 5 rr ?? < ?? + ?? (4) then one can have: r4 c4 fb c4 iiii =+ (5) the downward slope of the v fb ripple can be estimated as: out slope1 v v r4 c4 ? = (6) as one can see from equation (6), if there is instability in pwm mode, one can reduce either r4 or c4. if c4 can not be reduced further due to limitation from equation (4), then one can only reduce r4. from bench experiments, vslope1 is expected to be around 20~40v/ms. in the case of poscap or other types of capacitor with higher esr, the external ramp is not necessary. figure 7?simplified circuit in pwm mode without external ramp compensation figure 7 shows the equivalent circuit in pwm mode with the hs-fet off and without an external ramp circuit. the esr ripple dominates the output ripple. the downward slope of the v fb ripple is: ref slope1 esr v v l ? = (7) from equation (7), one can see that the downward slope of v fb ripple is proportional to esr/l. therefore, it?s necessary to know the minimum esr value of the output capacitors when no external ramp is used. there is also a limitation with inductance in this case. the smaller the inductance, the more stable it will be. from our bench experiments, it is recommended to keep vslope1 around 15~30v/ms. while in skip mode, the downward slope is not related to the external ramp. in skip mode, the downward slope of the v fb ripple is the same whether the external ramp is used or not. figure 8 shows an equivalent circuit with hs-fet off and the current modulator regulating the ls-fet. the downward slope of the v fb ripple can be determined as follows (i mod is ignored here): () ref slope2 12 out v v rr c ? = + (8) i mod figure 8?simplified circuit in skip mode to keep the system stable during light load condition, the values of the fb resistors should not be too big. it is recommended to keep the v slope2 value around 0.4~0.8mv/ms. it should be noted that imod is excluded from the equation because it does not impact the system?s stability at light load conditions. bootstrap charging the floating power mosfet driver is recommended to be powered by an external v cc through d2 as shown in figure 9. this floating driver has its own uvlo protection. this uvlo?s rising threshold is 2.2v with a hysteresis of 150mv. u1 will regulate to maintain bst voltage across c4 if (v cc -v sw ) is less than 3.5v. the recommended external bst diode d2 is in4148, and the bst cap c4 is 0.1~1 f.
nb639 ? high efficiency, fast transie nt synchronous step-down converter nb639 rev.1.13 www.monolithicpower.com 12 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. v in v out d1 m1 bst vcc c4 d2 l1 sw u1 3.5v c2 figure 9?bootstrap charging circuit soft start/stop the nb639 employs soft start/stop (ss) mechanism to ensure smooth output during power-up and power shutdown. when the en pin becomes high, an internal current source (8.5 a) charges up the ss cap. the ss cap voltage takes over the v ref voltage to the pwm comparator. the output voltage smoothly ramps up with the ss voltage. once the ss voltage reaches the same level as the ref voltage, it keeps ramping up while ref takes over the pwm comparator. at this point, the soft start finishes and it enters into steady state operation. when the en pin becomes low, the ss cap voltage is discharged through an 8.5 a internal current source. once the ss voltage reaches ref voltage, it takes over the pwm comparator. the output voltage will decrease smoothly with ss voltage until zero level. the ss cap value can be determined as follows: ss ss ss ref t(ms)i(a) c(nf) v(v) = (9) if the output capacitors have large capacitance value, it?s not recommended to set the ss time too small. a minimal value of 4.7nf should be used if the output capacitance value is larger than 330uf. power good (pgood) the nb639 has power-good (pgood) output. the pgood pin is the open drain of a mosfet. it should be connected to v cc or other voltage source through a resistor (e.g. 100k). after the input voltage is applied, the mosfet is turned on, so that the pgood pin is pulled to gnd before ss ready. after fb voltage reaches 90% of ref voltage, the pgood pin is pulled high after a delay. the pgood delay time is determined as follows: pgood ss t (ms) 0.5 t (ms) 0.5 = + (10) when the fb voltage drops to 85% of the ref voltage, the pgood pin will be pulled low. over-current protection (ocp) and short- circuit protection (scp) the nb639 has cycle-by-cycle over-current limit control. the inductor current is monitored during the on state. once it detects that the inductor current is higher than the current limit, the hs- fet is turned off. at the same time, the ocp timer is started. the ocp timer is set as 40 s. if in the following 40 s, the current limit is hit for every cycle, then it?ll tri gger ocp. the converter needs power cycle to restart after it triggers ocp. when the current limit is hit and the fb voltage is lower than 50% of the ref voltage, the device considers this as a dead short on the output and triggers ocp immediately. this is short circuit protection (scp). over/under-voltage protection (ovp/uvp) the nb639 monitors the output voltage through a resistor divider feedback (fb) voltage to detect overvoltage and undervoltage on the output. when the fb voltage is higher than 125% of the ref voltage, it?ll trigger ovp. once it triggers ovp, the ls-fet is always on while the hs-fet is always off. it needs power cycle to power up again. when the fb voltage is below 50% of the ref voltage (0.815v), uvp will be triggered. usually, uvp accompanies a hit in current limit and this results in scp. uvlo protection the nb639 has under-voltage lock-out protection (uvlo). when v cc is higher than the uvlo rising threshold voltage, the nb639 will be powered up. it shuts off when v cc is lower than the uvlo falling threshold voltage. this is non- latch protection.
nb639 ? high efficiency, fast transie nt synchronous step-down converter nb639 rev.1.13 www.monolithicpower.com 13 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. thermal shutdown thermal shutdown is employed in the nb639. the junction temperature of the ic is internally monitored. if the junction temperature exceeds the threshold value (typically 150oc), the converter shuts off. this is non-latch protection. there is about 25oc hysteresis. once the junction temperature drops to around 125oc, it initiates a soft start.
nb639 ? high efficiency, fast transie nt synchronous step-down converter nb639 rev.1.13 www.monolithicpower.com 14 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. application information setting the output voltage the output voltage is set by using a resistor divider from the output voltage to fb pin. when there is no external ramp employed, the output voltage is set by feedback resistors r1 and r2. first, choose a value for r2. a value within 5k ? -40k ? is recommended to ensure stable operation. then, r1 is determined as follows: out ref ref vv r1 r2 v ? = (11) when low esr ceramic capacitor is used in the output, an external voltage ramp should be added to fb through resistor r4 and capacitor c4.the output voltage is influenced by ramp voltage v ramp except r divider. the v ramp can be calculated as shown in equation 19. choose a value within 5k ? -40k ? for r2. the value of r1 then is determined as follows: ref ramp out ref ramp 1 r1 1 vv 1 2 1 r4 r2 v v v 2 = + ? ?? ?? ?? ?? (12) using equation 12 to calculate the output voltage can be complicated. furthermore, as v ramp changes due to changes in v out and v in , v fb also varies. to improve the output voltage accuracy and simplify the calculation of r2 in equation 12, a dc-blocking capacitor cdc can be added. figure 10 shows a simplified circuit with external ramp compensation and a dc-blocking capacitor. with this capacitor, r1 can easily be obtained by using equation 11. cdc is suggested to be 1-4.7 f for better dc blocking performance. figure 10?simplified circuit with external ramp compensation and dc-blocking capacitor. input capacitor the input current to the step-down converter is discontinuous. therefore, a capacitor is required to supply the ac current to the step-down converter while maintaining the dc input voltage. ceramic capacitors are recommended for best performance. in the layout, it?s recommended to put the input capacitors as close to the in pin as possible. the capacitance varies significantly over temperature. capacitors with x5r and x7r ceramic dielectrics are recommended because they are fairly stable over temperature. the capacitors must also have a ripple current rating greater than the maximum input ripple current of the converter. the input ripple current can be estimated as follows: out out cin out in in vv ii (1 ) vv = ? (13) the worst-case condition occurs at: out cin i i 2 = (14) for simplification, choose the input capacitor whose rms current rating is greater than half of the maximum load current. the input capacitance value determines the input voltage ripple of the converter. if there is input voltage ripple requirement in the system design, choose the input capacitor that meets the specification.
nb639 ? high efficiency, fast transie nt synchronous step-down converter nb639 rev.1.13 www.monolithicpower.com 15 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. the input voltage ripple can be estimated as follows: out out out in sw in in in iv v v(1) fc v v = ? (15) the worst-case condition occurs at v in = 2v out , where: out in sw in i 1 v 4f c = (16) output capacitor the output capacitor is required to maintain the dc output voltage. ceramic or poscap capacitors are recommended. the output voltage ripple can be estimated as: out out out esr sw in sw out vv 1 v(1)(r ) fl v 8fc = ? + (17) where r esr is the equivalent series resistance (esr) of the output capacitor. in the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. the output voltage ripple is mainly caused by the capacitance. for simplification, the output voltage ripple can be estimated as: out out out 2 in sw out vv v(1) v 8f lc = ? (18) the output voltage ripple caused by esr is very small. therefore, an external ramp is needed to stabilize the system. the voltage ramp is expected to be around 30mv. the external ramp can be generated through resistor r4 and capacitor c4 using the following equation: in out on ramp (v v ) t v r4 c4 ? = (19) the c4 should be chosen so that it meets the following condition: 12 sw 1 2 rr 11 () 2f c45rr < + (20) in the case of poscap capacitors, the esr dominates the impedance at the switching frequency. the ramp voltage generated from the esr is high enough to stabilize the system. therefore, an external ramp is not needed. a minimum esr value of 12m ? is required to ensure stable operation of the converter. for simplification, the output ripple can be approximated as: out out out esr sw in vv v(1)r fl v = ? (21) inductor the inductor is required to supply constant current to the output load while being driven by the switching input voltage. a larger value inductor will result in less ripple current that will result in lower output ripple voltage. however, a larger value inductor will have a larger physical size, higher series resistance, and/or lower saturation current. a good rule for determining the inductor value is to allow the peak-to-peak ripple current in the inductor to be approximately 30~40% of the maximum switch current limit. also, make sure that the peak inductor current is below the maximum switch current limit. the inductance value can be calculated as: out out sw l in vv l(1) fi v =? (22) where i l is the peak-to-peak inductor ripple current. choose an inductor that will not saturate under the maximum inductor peak current. the peak inductor current can be calculated as: out out lp out sw in vv ii (1 ) 2f l v =+ ? (23)
nb639 ? high efficiency, fast transie nt synchronous step-down converter nb639 rev.1.13 www.monolithicpower.com 16 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. table 1?inductor selection guide part number manufacturer inductance (h) dcr (m ? ) current rating (a) dimensions l x w x h (mm 3 ) switching frequency (khz) pcmc-135t-r68mf cyntec 0.68 1.7 34 13.5 x 12.6 x 4.8 600 fda1254-1r0m toko 1 2 25.2 13.5 x 12.6 x 5.4 300~600 fda1254-1r2m toko 1.2 2.05 20.2 13.5 x 12.6 x 5.4 300~600 typical design parameter tables the following tables include recommended component values for typical output voltages (1.05v, 1.2v, 1.8v, 2.5v, 3.3v) and switching frequencies (300khz, 500khz, and 700khz). refer to tables 2-4 for design cases without external ramp compensation and tables 5-7 for design cases with external ramp compensation. external ramp is not needed when high-esr capacitors, such as electrolytic or poscaps are used. external ramp is needed when low-esr capacitors, such as ceramic capacitors are used. for cases not listed in this datasheet, a calculator in excel spreadsheet can also be requested through a local sales representative to assist with the calculation. table 2?300khz, 12 v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r freq (k ? ) 1.05 2.2 12.1 43 301 1.2 2.2 12.1 24 360 1.8 2.2 19.6 15.8 499 2.5 2.2 30 14.7 680 3.3 2.2 40.2 13.3 806 table 3?500khz, 12 v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r freq (k ? ) 1.05 1 12.1 43 180 1.2 1 12.1 24 200 1.8 1 19.6 15.8 309 2.5 1 30 14.7 402 3.3 1 40.2 13.3 523 table 4?700khz, 12 v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r freq (k ? ) 1.05 1 12.1 43 120 1.2 1 12.1 24 140 1.8 1 19.6 15.8 210 2.5 1 30 14.7 309 3.3 1 40.2 12.4 402 table 5?300khz, 12 v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r4 (k ? ) c4 (pf) r freq (k ? ) 1.05 2.2 12.1 43 330 220 301 1.2 2.2 12.1 24 330 220 360 1.8 2.2 19.6 15.2 499 220 499 2.5 2.2 30 14.7 499 220 680 3.3 2.2 40.2 13 604 220 806 table 6?500khz, 12 v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r4 (k ? ) c4 (pf) r freq (k ? ) 1.05 1 12.1 43 330 220 180 1.2 1 12.1 24 330 220 196 1.8 1 19.6 15.8 330 220 309 2.5 1 30 14.7 383 220 402 3.3 1 40.2 12 499 220 522 table 7?700khz, 12 v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r4 (k ? ) c4 (pf) r freq (k ? ) 1.05 1 12.1 43 220 220 120 1.2 1 12.1 24 220 220 140 1.8 1 19.6 15.8 261 220 210 2.5 1 30 14.3 261 220 270 3.3 1 40.2 12 360 220 383
nb639 ? high efficiency, fast transie nt synchronous step-down converter nb639 rev.1.13 www.monolithicpower.com 17 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical application figure 11 ? typical application circuit with low esr ceramic capacitor figure 12 ? typical application circuit with no external ramp figure 13 ? typical application circuit with low esr ceramic capacitor and dc-blocking capacitor .
nb639 ? high efficiency, fast transie nt synchronous step-down converter nb639 rev.1.13 www.monolithicpower.com 18 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. layout recommendation 1. the high current paths (gnd, in, and sw) should be placed very close to the device with short, direct and wide traces. 2. put the input capacitors as close to the in and gnd pins as possible. 3. put the decoupling capacitor as close to the v cc and gnd pins as possible. 4. keep the switching node sw short and away from the feedback network. 5. the external feedback resistors should be placed next to the fb pin. make sure that there is no via on the fb trace. 6. keep the bst voltage path (bst, c bst, and sw) as short as possible. 7. keep the bottom in and sw pads connected with large copper to achieve better thermal performance. 8. four-layer layout is strongly recommended to achieve better thermal performance. r3 c3 p g o o d f r e q a g n d 1 6 1 5 1 4 1 3 1 2 1 1 1 2 3 4 5 6 e n s s p g n d f b s w i n p g n d p g n d p g n d p g n d p g n d c6 r3 r3 r5 r6 c6 i n i n s w c6 d2 top layer s inner1 layer gnd inner2 layer bottom layer figure 14?pcb layout
nb639 ? high efficiency, fast transie nt synchronous step-down converter notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. nb639 rev. 1.13 www.monolithicpower.com 19 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. package information qfn20 (3x4mm)

▲Up To Search▲

Price & Availability of NB639DL

	To Download NB639DL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .